How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Silvaco, Inc.
Category:
DDR
AXI External Memory Controller
The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (S…
Overview
The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (SRAM, Flash, etc.). The number of read wait states, the number of write wait states, and the memory width are all configurable through the APB register interface of the EBI. The EBI allows word, half-word, and byte width addressing to 64-bit, 32-bit, 16-bit, and 8-bit external devices.
Key features
- Interfaces AXI bus to external SRAM or Parallel Flash devices
- AMBA® AXI Compatible
- Supports 8-bit, 16-bit, 32-bit and 64-bit external modes
- Supports byte (8-bit), halfword (16-bit), word (32-bit) and dword (64-bit) internal accesses
- Independent programmable wait states per device interface
- Selects up to 4 external devices
Block Diagram
AXI External Memory Controller block diagram
What’s Included?
- Verilog Source
- Complete Test Environment
- AXI Bus Functional Model
- C-Sample Code
Specifications
Identity
Part Number
70187
Vendor
Silvaco, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United States
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR IP Hardening - Overview & Advance Tips
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is AXI External Memory Controller?
AXI External Memory Controller is a DDR IP core from Silvaco, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.