What is DDR3 SDRAM Memory Controller?
DDR3 SDRAM Memory Controller is a DDR IP core from Xylon listed on Semi IP Hub.
Vendor:
Xylon
Category:
DDR
DDR3 SDRAM Memory Controller
The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller …
Overview
The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller that supports industry standard Double Data Rate 3 (DDR3) SDRAM memories on AMD-Xilinx 7 Series FPGAs/SoCs. Its system interface is compliant to ARM’s AMBA® Advanced eXtensible Interface (AXI4) protocol.
“Easy-to-use” parameters and the synthesis for different requirements, optimized for area and speed, auto-routed design makes this IP Core especially suitable for AMD-Xilinx 7 Series FPGA/SoC designs featuring AXI4 bus architecture. It enables an easy connection of processor cores, as well as various peripheral cores, to DDR3 memory chips via AXI4 slave system interface port.
The logiMEM IP Core is fully embedded into the AMD-Xilinx Vivado toolset, and its parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiMEM can be smoothly integrated with other logicBRICKSTM IP cores for building of advanced GUI embedded systems.
“Easy-to-use” parameters and the synthesis for different requirements, optimized for area and speed, auto-routed design makes this IP Core especially suitable for AMD-Xilinx 7 Series FPGA/SoC designs featuring AXI4 bus architecture. It enables an easy connection of processor cores, as well as various peripheral cores, to DDR3 memory chips via AXI4 slave system interface port.
The logiMEM IP Core is fully embedded into the AMD-Xilinx Vivado toolset, and its parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiMEM can be smoothly integrated with other logicBRICKSTM IP cores for building of advanced GUI embedded systems.
Key features
- Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
- Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
- 800 Mb/s max bandwidth on Artix-7/Spartan-7 devices (-1, -1L, -1LI speed grades)
- x8/x16 DDR3 SDRAM component data width support
- x8/x16/x32 DDR3 interface data width support
- AXI4 Slave Interface on system side (fabric)
- Supports single-beat and burst transaction on the AXI4 interface bus
- 8:1 system data width to DDR3 data width ratio
- 4:1 memory to FPGA system interface clock ratio
- Programmable burst length on AXI interface, on both read and write memory cycles
- Programmable CAS Latency (supports CL5 and CL6)
- Supported for both DDR3 (1.5V) and DDR3L (1.35V)
Block Diagram
logiMEM block diagram
Applications
- Video systems and image processing
- Embedded computing
- Communication and Networking equipment
- High performance peripheral equipment
What’s Included?
- Encrypted VHDL in a JAR Deliverable that comes with documentation
Specifications
Identity
Part Number
logiMEM
Vendor
Xylon
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR3
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Croatia
Frequently asked questions about DDR Interface IP
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.