Vendor: NTLab Category: DDR

1 Gbps DDR LVDS transmitter

065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmit…

Controller TSMC 65nm GP Silicon Proven View all specifications

Overview

065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmitter. There are other two internal pins (VREF_TX and IREF_TX) to get voltage reference and current reference. PAD_OUTp and PAD_OUTn are complementary outputs to connect to the bonding pads. The block conforms to TIA/EIA-644 LVDS standards without hysteresis.

Key features

  • TSMC CMOS 0.065 um
  • 2.5 V analog power supply
  • 1.2 V digital power supply
  • 1.2 V CMOS input logic signals
  • 4-step (2-bit) adjustable transmitter output current range (from 1.75 mA to 7.0 mA)
  • 1 Gbps (DDR MODE) switching rates
  • Conforms to TIA/EIA-644 LVDS standards without hysteresis
  • Temperature range: -40 °C to + 125 °C
  • Optimized for pad-limited layout design
  • Portable to other technologies (upon request)

Block Diagram

Applications

  • Point-to-point data transmission
  • Multidrop buses
  • Clock distribution
  • Backplane data transmission
  • Cable data transmission

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentationn

Silicon Options

Foundry Node Process Maturity
TSMC 65nm GP Silicon Proven

Specifications

Identity

Part Number
065TSMC_LVDS_05
Vendor
NTLab
Type
Silicon IP
Controller / PHY
Controller

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is 1 Gbps DDR LVDS transmitter?

1 Gbps DDR LVDS transmitter is a DDR IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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