IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
MIPI PHY
MIPI D-PHY TX
This is a D-PHY Master IP compliant with the “MIPI Alliance Spec for D-PHY v1.2”.
Overview
This is a D-PHY Master IP compliant with the “MIPI Alliance Spec for D-PHY v1.2”. The IP consists of 1 clock and 4 data lanes. Each data lane supports HS and LP Escape modes (LPDT, Trigger, ULPS) in the forward direction. The supported data rate per lane is 2.5 Gbps in High-Speed mode and 10 Mbps in Low-Power escape mode. Only data lane 0 is bi-directional and additionally supports Turnaround and LP Escape modes (LPDT and Trigger) in the reverse direction. Target applications are CSI-2 devices and DSI host physical layers.
Key features
- Data rate per lane: High-Speed mode 80 Mbps to 2.5 Gbps, Low-Power mode 10 Mbps
- Compliant with the MIPI D-PHY spec v1.2
- Support for HiSPi-SLVS TX compatible mode
- Lane type: 1 clock + 4 data lanes (D0 is bi-directional)
- On-chip differential 100Ω terminations with calibration
- Support for D-PHY Ultra Low Power State
- Built-in self-test function
Block Diagram
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Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 22nm | FDX | Silicon Proven |
Specifications
Identity
Part Number
MIPI D-PHY TX
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY
Standards & Interfaces
Compliance Status
Compliant
MIPI PHY
MIPI D-PHY
Files
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Provider
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Frequently asked questions about MIPI PHY IP
What is MIPI D-PHY TX?
MIPI D-PHY TX is a MIPI PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.