MIPI D-PHY RX
This is a D-PHY RX IP compliant with the “MIPI Alliance Spec for D-PHY v1.2”.
Overview
This is a D-PHY RX IP compliant with the “MIPI Alliance Spec for D-PHY v1.2”. The IP consists of 1 clock and 4 data lanes. Data lane 0 supports HS and ULPS modes in the forward direction, and also supports LP Escape modes (LPDT, Trigger) and Turnaround in both forward and reverse directions. Other Data lanes support HS and LP Escape modes (LPDT, Trigger, ULPS) in the forward direction. Each lane supports a maximum of 2.5 Gbps in High-Speed mode and 10 Mbps in Low-Power escape mode. Target applications are CSI-2 host and DSI device physical layers.
Key features
- Compliant with the MIPI D-PHY spec v1.2
- Data rate per lane: High-Speed mode 80 Mbps to 2.5 Gbps, Low-Power mode 10 Mbps
- Lane type:1 clock + 4 data lanes (D0 lane is bi-directional)
- All lanes support D-PHY HS and ULPS modes in the forward direction
- All data lanes support Escape mode (LPDT, Trigger) in the forward direction
- D0 lane supports reverse Escape modes (LPDT, Trigger) and Turnaround
- All lanes support SUB-LVDSRX mode
- On-chip differential 100Ω terminations with calibration
- Built-in self-test function
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 22nm | FDX | Silicon Proven |
Specifications
Identity
Standards & Interfaces
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about MIPI PHY IP
What is MIPI D-PHY RX?
MIPI D-PHY RX is a MIPI PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.