Memory interface IP cores provide the critical connectivity layer between processing elements and memory devices, enabling high-bandwidth, low-latency, and power-efficient data access in modern SoC, ASIC, AI, networking, and high-performance computing designs.
This category includes DDR, LPDDR, GDDR, HBM, NAND Flash, and NOR Flash interface IP solutions, covering memory controllers, PHYs, controller-PHY subsystems, training engines, calibration logic, and complete memory interface architectures. These IP cores are designed to maximize memory bandwidth, optimize latency, ensure signal integrity, and simplify integration across advanced semiconductor process nodes.
TSMC CLN16FFCLL 16nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
High Performance DDR 3/2 Memory Controller IP
This memory controller supports DDR2/3 SDRAM.
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
The DDR (Double Data Rate) controller IP is for LPDDR4 and DDR4/3/3L optimized for low latency.
DDR 4/3 Memory Controller IP - 2400MHz
This memory controller supports DDR3/4 SDRAM.
The GDDR6 controller core is designed for use in applications requiring high memory throughput including graphics, driver assista…
The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput.
NAND Host Controller provides an easy interface to access NAND Flash Memory devices.
1 Gbps DDR rail to rail LVDS receiver
LVDS_RX is LVDS receiver with rail to rail input range.
065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmit…
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias.
High-bandwidth graphics memory controller for GPUs and AI accelerators
Truechip's Verification IP (VIP) for DFI provides an effective and efficient way to verify the components interfacing with the DFI interface of an ASIC/FPGA or SoC.