How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
NTLab
Category:
DDR
1 Gbps DDR rail to rail LVDS receiver
LVDS_RX is LVDS receiver with rail to rail input range.
Overview
LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTp, OUTn) to receive data and the control pins (EN_RX, EN_RES) to configure the state of the receiver. EN_RES enables the on-chip 100 Ohm resistor. The VREF12 is input voltage reference. Pin IREF_RX to get current reference from receiver bias. PAD_INp and PAD_INn are complementary input to connect to the bonding pads.
Key features
- TSMC CMOS 0.065 um
- 2.5 V analog power supply
- 1.2 V digital power supply
- 1.2 V CMOS input and output logic signals
- 1 Gbps (DDR MODE) switching rates
- Conforms to TIA/EIA-644 LVDS standards without hysteresis
- Rail to rail input range
- Temperature range: -40 °C to + 125 °C
- Optimized for pad-limited layout design
- Portable to other technologies (upon request)
Block Diagram
065TSMC_LVDS_06 block diagram
Applications
- Point-to-point data receiver
- Multidrop buses
- Clock distribution
- Backplane receiver
- Backplane data receiver
- Cable data receiver
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | GP | Silicon Proven |
Specifications
Identity
Part Number
065TSMC_LVDS_06
Vendor
NTLab
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
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Frequently asked questions about DDR Interface IP
What is 1 Gbps DDR rail to rail LVDS receiver?
1 Gbps DDR rail to rail LVDS receiver is a DDR IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.