LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller
The LPDDR4 and LPDDR5 combo controller core is designed for use in applications requiring high memory throughput at low power inc…
- Controller
- LPDDR4 + 1
LPDDR Interface IP cores provide the controller, PHY, and training technologies required to connect SoCs and ASICs to low-power DRAM, enabling high memory bandwidth while minimizing energy consumption in power-sensitive applications.
This category includes IP solutions supporting LPDDR4, LPDDR5, LPDDR5X, and LPDDR6 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, initialization and training engines, power management features, ECC capabilities, and advanced signal integrity technologies optimized for mobile, AI, automotive, and edge computing platforms.
LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller
The LPDDR4 and LPDDR5 combo controller core is designed for use in applications requiring high memory throughput at low power inc…
M31 LPDDR4X multi-PHY support DDR4, LPDDR4, and LPDDR4X up to 4267Mbps.
The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DD…
Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern co…
The DDR PHY is designed to support LPDDR4, LPDDR4x and LPDDR5 SDRAM.
With sophisticated architecture and technology, the Vendor provides LPDDR4/4x IP solution with high performance and low power.
The LPDDR4X Verification IP provides an effective & efficient way to verify the components interfacing with the LPDDR4X interface…
Compatible with LPDDR4X, with a maximum rate up to 4267Mbps; Compliant with DFI 4.0 for PHY and control interfaces
LPDDR4x Secondary/Slave (memory side!) PHY
This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products.
LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Controller ASIL B Compliant supporting LPDDR5X, LPDDR5 and LPDDR4X for Automotive Applications
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR4x/5 Secondary/Slave (memory side!) PHY
This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products.
LPDDR5X/5/4X PHY in Samsung (SF4X)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) an…
LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) an…
Compatible with JEDEC standards LPDDR4X , LPDDR5 and LPDDR5X SDRAMs; Supports for data transfer rate up to 8533Mbps
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…