LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package

The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. The controller connects to the LPDDR5X/5/4X PHY or other LPDDR5X/5/4X PHYs via the DFI 5.0 interface to create a complete memory interface solution. The LPDDR5X/5/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual channel support, as well as the DFI interface to the PHY.

The LPDDR Controller seamlessly integrates the Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. The Secure LPDDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the secure memory controllers is as low as 2 clock cycles.

• Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
• Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
• DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
• Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
• High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
• UVM testbench with embedded assertions and options to incorporate an LPDDR5X/5/4X PHY into a verification environment
• Secure Controller: Integrated IME Security Module for data confidentiality