LPDDR PHY and Controller

A Family of High-Speed On-Chip Memory Interface IP

The Cadence PHY and Controller for LPDDR6/5X/5/4X/4/3 is a family of high-speed on-chip memory interface IP that satisfy high-performance requirements with products that are optimized for each application's needs.

The latest LPDDR6/5X PHY and Controller IP support the newest JEDEC Low-Power Double Data Rate DRAM (LPDDR6) standard with data rates of up to 14.4Gbps, up to 50% faster than the previous generation. The LPDDR6/5X IP product line is a new high-speed architecture that is based on Cadence’s industry-leading LPDDR5X 10.7Gbps and GDDR6 22Gbps products. The architecture targets high-performance and artificial intelligence (AI) applications. The high-performance design features dynamic feedback equalization (DFE), feed forward equalization (FFE), and continuous time linear equalization (CTLE), as well as per-bit read and write delay adjustment. Cadence’s proprietary ultra-low jitter clock trees and DLLs, proven in the GDDR6 22Gbps product line, contribute to better system timing margins, lower cost package and PCB designs, and overall system reliability. Multiple low-power modes and configurations are supported and target industry-leading exit latencies, multiple frequency set points (FSP), and dynamic frequency scaling (DFS) in hardware.

The LPDDR6/5X IP products are designed to integrate easily into AI and data center applications. The PHY IP can be delivered as either firm or hard macros, supporting multiple floorplan and bump map options. The PHY top-level logic uses low clock frequencies to enable easier, faster, and more reliable timing closure.

The LPDDR Controller delivers a wide array of capabilities to address emerging LPDDR DRAM subsystem RAS, ECC, parity, and data-scrubbing functions. The application-optimized LPDDR6 PHY and Controller can achieve industry-leading data rates, with low-power features that include multiple low-power states for longer battery life and greener operation.

PHY

• Application-optimized configurations for fast time to delivery and lower risk
• Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
• I/O pads with impedance calibration logic and data-retention capability
• Fine-grain custom delay cell for delay tuning
• Internal and external datapath loop-back modes
• RX and TX equalization for heavily loaded systems
• Programmable per-bit (PVT compensated) deskew on read and write datapaths
• Multiple floor plans

Controller

• Memory controller interface complies with DFI standard
• Application-optimized configurations for fast time to delivery and lower risk
• Supports advanced RAS features including error scrubbing, parity, etc.
• Compliant to LPDDR6/5X/4X/4/3 protocol memories
• Priority per command on Arm^®AMBA^® 4 AXI, AMBA 3 AXI
• Single and multi-port host interface options
• QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces

• High Performance: For AI/ML and targeted data center applications
• Low Power and Area: Industry-leading PPA based on advanced architecture and implementation
• Reliable: Maximum system margin with advanced clocking and I/O architectures