Low Power All Digital Fractional-N PLL in Samsung 14LPP

Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area. It is suitable for IoT and embedded clocking applications in systems running below the nominal core voltage at frequencies up to 1.5GHz. It is suitable as a clock source for moderate speed microprocessor blocks and other logic.

To give IoT designers the maximum flexibility in managing power, pPLL05 is very small (< 0.008 sq mm) and low power (< 0.6mW). It is well suited to applications with a single low voltage power supply that the PLL shares with the blocks that use its output clock. Better jitter performance can be achieved if the pPLL05 has its own analog power supply.

pPLL05 integrates easily into any SoC design and includes all the views and models required by back end flows.

The pPLL05 is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.

pPLL05 can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.

Perceptia further provides integration support and offers customization and migration services.

• Low power, suitable for IoT applications
• Good jitter, suitable for clocking digital logic.
• Extremely small die area (< 0.005 sq mm), using a ring oscillator
• Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
• Reference clock from 5MHz to 200MHz
• Second-generation digital PLL architecture, providing integer and fractional multiplication
• Primary PLL output running at the main DCO frequency for lowest noise clocking
• Two further PLL outputs via separate postscalers
  • Post-scalers programmable from 1 to 2,040
• Lock-detect output
• Can generate a spread-spectrum clock from a clean reference
• Oscillator output duty cycle better than 48 / 52%
• Highly testable using industry standard flows
  •   ATPG vectors provided
  •   Specification of functional tests to supplement ATPG testing

• Small size  (< 0.008 sq mm)
• Low Power (< 0.6 mW)
• Easy integration
• Fractional Multiplication

• IoT
• Embedded
• Moderate speed digital systems

• Datasheet
• Detailed Verilog behavioral model
• Timing models
• LEF5.6 abstract for floor planning/chip assembly
• Integration Guide
• DFT Guide
• Integration support
• Characterization report
• GDSII layout macrocell
• CDL netlist for LVS
• DRC, LVS and SI verification reports
• Netlist model with accompanying documentation allowing integration of the module in scan chains