The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
- UMC
- 55nm
- LP
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Enhancement) Logic Process
UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Proce…
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process
XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process
Ultral-small size: 0.033mm2; High performance, low EMI TX driver design
EDP_RX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP RX.
LVDS 10 bits dual port transmitter
IP
USB 2.0 Device PHY IP, UMC 0.11um eFlash process
UMC 0.11um eFlash Process , USB 2.0 OTG PHY
LVDS RX, UMC 40nm LP/RVT Low-K Logic process.
The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channel…
PCIe 2.1 PHY(12nm,14nm, 16nm, 28nm, 40nm, 55nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
SMIC 130nm G LVDS 800Mbps Transmitter
IP
SMIC 130nm G LVDS 1.25Gbps Transmitter
IP