ST28nm LVDS Transmitter

The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution. The IP converts 70-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks via a dedicated pin.

• Supports 20MHz ~ 150MHz clock
• 35:5 data channel compression ratio at up to 1050Mbps per channel data rate
• Supports single pixel and dual pixel interfaces
• Converts 70 bits data to 10-pair LVDS data stream
• No special start-up sequence required between clock/data and PD pins
• Supports Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread
• No external component required for PLL
• Clock edge selectable
• Compatible with the TIA/EIA-644-A LVDS standard