The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
- PHY
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
This 1-lane to 4-lane PCIE PHY includes all high-speed analog functions for high-speed data transport between chips over PCBs and…
The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…
Automotive (AP) version of the DWC Enterprise PCS.
The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…
25G Automotive (AC) version of the Enterprise / XLG PCS
The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…
LVDS Driver/Buffer
LVDS Receiver
LVDS Transmitter
High Speed Ethernet Quad 10G to 100G PCS
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet Gen-2 Quad 100G PCS IP
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet 4/2/1-Lane 100G PCS
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet 2/4/8-Lane 200G/400G PCS
The Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a set of fe…
112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
The 112G Ethernet PHY IP, an integral part of the 400GbE/800GbE Ethernet solution enables long reach (LR), medium reach (MR), ver…
PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, SS SF4X x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, SS SF2 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY G2 , TSMC N5 x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …