Vendor: Synopsys, Inc. Category: Single-Protocol PHY

Enterprise Ethernet PCS IP

The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…

Overview

The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Medium Attachment Sublayer (PMA) through a Media Independent Interface (MII). The ASIL B Ready ISO 26262 certified Enterprise Ethernet PCS Controller IP is available with an automotive safety package.

The Enterprise Ethernet PCS Controller IP supports the following functions as per IEEE 802.3 and 25G consortium specifications (for 25G and 50G modes):

PCS sub layer functions

PMA sub layer functions

FEC functions

Link Training

Auto Negotiation

Host Interface via APB3

The IP supports the following link types through the PMA layer:

10GBASE-R

25GBASE-CR

25GBASE-CR-S

25GBASE-KR

25GBASE-KR-S

40GBASE-R

40GBASE-KR4

50GBASE-CR2

50GBASE-KR2

100GBASE-CR4

100GBASE-KR4

As the leading supplier of Ethernet IP, Synopsys provides designers with a high-performance, easily-configurable Enterprise Ethernet IP solution. Synopsys’ expertise in developing and supporting Ethernet IP offers a low-risk, high-quality enterprise Ethernet IP solution with optimized configurations for a range of applications. The Enterprise Ethernet PCS Controller IP is verified using state-of-the-art methodologies including the RTL design, verification, hardware verification and interoperability tests. It can be easily configured with a user-friendly application interface to accomplish functional and implementation objectives and meet design requirements. Coupled with the configurable Enterprise Ethernet MAC Controller IP and the Multi-Protocol 25G PHY supporting Ethernet, Synopsys provides designers with a complete solution for Enterprise Ethernet designs.

The Ethernet IP solution includes configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.

Key features

  • Compliant with IEEE standards including:
    • IEEE 802.3-2015 Clause 45, 46, 49, 69, 72, 73, 74, 81, 82, 83, 91, 92, and 93 (depending on configuration)
    • IEEE 802.3az-2010
    • IEEE 802.3ba-2010
    • IEEEP802.3by June 2016 Clause 45, 69, 73, 74, 78, 106, 107, 108, and 109 (depending on configuration)
    • IEEE 1588-2008 with 1-step timestamping
  • 25G Consortium specifications for 25G & 50G r1.6 (Oct 15, 2015)
  • Configurable for 10G, 25G, 40G, 50G and 100G Ethernet applications
  • Integration tested with the Synopsys Enterprise Ethernet MAC and Multi-Protocol PHYs
  • Comprehensive deliverables packaged in an IP-XACT compatible .run file
  • Includes Synopsys’s coreConsultant tool for easy configuration

Block Diagram

Specifications

Identity

Part Number
dwc_ether_xlgpcs
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Single-Protocol PHY IP

What is Enterprise Ethernet PCS IP?

Enterprise Ethernet PCS IP is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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