LVDS transmitter PHY
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
Overview
The LVDS transmitter is designed to support single link transmission between host and flat panel display with up to SXGA+ resolution. It also supports dual link transmission between host and flat panel display with up to UXGA resolution.
The IP converts 35-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks via a dedicated pin.
Key features
- Supports 25 MHz to 150 MHz clock
- 35:5 data channel compression ratio at up to 1050 Mbps per channel data rate
- Converts 35-bits data to 5-pair LVDS data streams
- No external component required for PLL
- Selectable clock edge
- Compatible with TIA/EIA-644-A LVDS standard
- Power down mode
- |VOD| is changeable from 50 mV to 400 mV
- Full industrial operating junction temperature range: -40°C to +125°C
Block Diagram
Specifications
Identity
Files
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Provider
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Frequently asked questions about Single-Protocol PHY IP
What is LVDS transmitter PHY?
LVDS transmitter PHY is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.