A design path to success exists for ultra-low-voltage SoCs

By C.H. Chien

September 15, 2026

Beyond low-power design and beyond multi-threshold-voltage libraries, clock and power gating, and voltage-frequency scaling lies the strange land of ultra-low-power systems. Here, power comes from tiny, semi-permanent batteries or energy scavenging, and it comes in microwatts or nanowatts, not milliwatts.

For system-on-chip (SoC) designers, this is the alien realm of ultra-low voltage (ULV): supply voltages near or below transistor threshold voltages. In this realm, many things are unfamiliar to conventional SoC designers. Foundational IP must be different. Familiar-looking tool flows may hide important differences in tools and skills. New challenges appear—threats that could sink a project.

ULV design explored

All differences in ULV design begin with the definition: ULV circuits use a V_DD near or below the threshold voltage of the process’s MOSFETs. This leads to several important effects.

First, of course, is energy savings, the whole reason for ULV design. ULV works because instantaneous power is quadratic in supply voltage. So, the instantaneous power consumed when a circuit is active, and hence the energy required to complete a task, can be significantly lower at lower V_DD.

Usually, designers will talk not about power consumption, but about the energy required to complete an operation, typically in nanoJoules. This is a preferred metric because, in ultra-low-power systems, ULV SoCs are usually quiescent for long periods, wake to perform specific tasks, and then reenter their trance. This activity pattern makes peak and average power figures poor indicators of energy consumption and, therefore, battery life or drain on energy scavengers.

But this energy benefit comes with challenges. Near threshold voltage, a MOSFET gate exerts only weak control over channel current. Leakage can be high, and the difference between I_ON and I_OFF is small.

Maintaining the separation—the values of 1 and 0—throughout each net’s stages and across clock trees becomes a fundamental undertaking for the design team. The separation is already low, and other factors conspire against it. Interconnect parasitics, noise, and process variations can prevent circuits from working reliably. So, ULV design requires special measures.

To read the full article, click here