Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 2…
An ADDLL operate at 50MHz~210MHz.
UMC 0.18um 9track Standard Cell Library, 1.8v operating voltage
UMC 0.18um Standard Cell Library
UMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon UMC 0.18um High-Speed Synchronous Memory Compiler optimized for United Microelectronics Corporation (UMC) 0.18um Logi…
UMC 0.18um process 1.8v/3.3v Generic IO library
RC oscillator 50MHz - UMC 0.18um
Fully integrated calibrated RC oscillator
16-Bit 40kS/s sigma-delta DAC - UMC 0.18um
16 bits 40kS/s sigma-delta DAC
Low-power bandgap - UMC 0.18um
Sub-voltage low-power bandgap reference circuit.
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II lo…
Low noise PLL operating at up to 3.25GHz (90nm UMC)
PSI3GRP_U9 is a low jitter PLL operating from 1GHz to 3.25GHz.
Wide range PLL operating from 135MHz to 945MHz (90nm UMC)
PSIWRP_U9 is a wide range PLL with the VCO operating from 175MHz to 945MHz.
Low spurs PLL operating at 1.296GHz (90nm UMC)
PSI1GLSP_U9 is a low spurs PLL operating at 1.296GHz.
Low noise PLL operating at 1.25GHz and 625MHz (90nm UMC)
PSI1GLP_U9 is a low jitter PLL operating at 1.
UMC 0.18um 1.8v 60MHz Ring Oscillator
The present IP is a Ring Oscillator which is controlled by the external 1.2v bandgap reference.
The present IP is a VCC Detector (VDT) circuit.
The present IP is a VCC Detector (VDT) circuit.