What is UMC 0.18um 3.3v APLL?
UMC 0.18um 3.3v APLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for umc.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
PLL
UMC 0.18um 3.3v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
Overview
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run at about 100MHz. By setting different values of DM(4:0) and DN(5:0) according to different REFin frequency, BAKo will be locked at the rising edge of REFin and the output frequency (Cko) will be locked at the multiples of the input frequency.
Key features
- Process: UMC 0.18um 1P4M/5M/6M CMOS process
- Supply voltage: 1.8v¡À10%
- Current: <3mA@1.8v
- Operating temperature: - 40c ~ +25c ~ +125c
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 180nm | BCD | — |
Specifications
Identity
Part Number
UMC18_PLL_02
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.