Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
SRAM
UMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon UMC 0.18um High-Speed Synchronous Memory Compiler optimized for United Microelectronics Corporation (UMC) 0.18um Logi…
Overview
VeriSilicon UMC 0.18um High-Speed Synchronous Memory Compiler optimized for United Microelectronics Corporation (UMC) 0.18um Logic 1P6M Generic II Salicide 1.8/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon UMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability.
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon UMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability.
Key features
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
- Tri-State Output(SRAM only)
- Write Mask Function(SRAM & Register File)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 180nm | BCD | Silicon Proven |
Specifications
Identity
Part Number
UMC18 MC
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
Learn more about SRAM IP core
Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
Why SRAM PUF Technology Is the Bedrock of Dependable Security in Any Chip
Vincent van der Leest, Synopsys
AI-driven SRAM demand needs integrated repair and security
Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
A comparison of SRAM vs quantum-derived semiconductor PUFs
This article explores the relative performance of SRAM PUF and quantum-derived semiconductor PUF technologies for IoT security.
Basics of SRAM PUF and how to deploy it for IoT security
This article covers the basics of what an SRAM PUF (physical unclonable function) is and how it works, as well as the functionality it offers in internet of things (IoT) security as the trust anchor for any device.
Frequently asked questions about SRAM IP cores
What is UMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler?
UMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for umc Silicon Proven.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.