UMC IP Cores

NO External-R ,frequency 32.768MHz , Oscillator .

• UMC
• 55nm
• ULP
• Pre-Silicon

NO External-R ,frequency 32.768KHz , Oscillator .

• UMC
• 55nm
• ULP
• Pre-Silicon

Internal-RC, trimmable fixed frequency 1MHz.

• UMC
• 110nm
• HS
• Pre-Silicon

Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.

• UMC
• 55nm
• SP
• Pre-Silicon

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process

• UMC
• 28nm
• HPC

Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.

• UMC
• 40nm
• LP
• Pre-Silicon

UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.

• UMC
• 55nm
• LP
• Pre-Silicon

DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Enhancement) Logic Process

• UMC
• 110nm
• HS
• Pre-Silicon

1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process

• UMC
• 110nm
• HS
• Pre-Silicon

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of…

• UMC
• 40nm
• LP
• Pre-Silicon

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,U…

• UMC
• 28nm

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,U…

• UMC
• 28nm
• Pre-Silicon

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,U…

• UMC
• 28nm

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,…

• UMC
• 28nm
• Pre-Silicon

Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,…

• UMC
• 28nm

Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of…

• UMC
• 40nm
• LP
• Pre-Silicon

Input 50M-210MHz, output 50M-210MHz.

• UMC
• 40nm
• LP
• Pre-Silicon

Input 10M-70MHz, output 10M-70MHz.

• UMC
• 40nm
• LP
• Pre-Silicon

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 2…

• UMC
• 28nm

Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process.

• UMC
• 55nm
• SP
• Pre-Silicon