UMC IP Cores

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• Pre-Silicon

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 130nm
• HS
• Silicon Proven

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 130nm
• HS
• In Production

Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Enhancement) Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 110nm
• HS
• Pre-Silicon

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

• Controller
• DDR2
• UMC
• 65nm
• LP
• Silicon Proven

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

• Controller
• DDR2
• UMC
• 130nm
• HS
• Pre-Silicon

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• SP
• Silicon Proven

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 65nm
• Silicon Proven

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• SP
• Pre-Silicon

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 65nm
• Pre-Silicon

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• In Production

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

• Controller + PHY + 1
• DDR2
• UMC
• 130nm
• HS
• Silicon Proven

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 130nm
• HS
• Pre-Silicon

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• SP
• Silicon Proven

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 65nm
• Silicon Proven

Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Enhancement) Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 110nm
• HS
• Pre-Silicon

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process

• Controller
• DDR2
• UMC
• 65nm
• LP
• Silicon Proven

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process

• Controller
• DDR2
• UMC
• 130nm
• HS
• Pre-Silicon

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• Silicon Proven

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 65nm
• Silicon Proven