The Platform Based SOC Design that Utilizes Structured ASIC Technology
The Platform Based SOC Design that Utilizes Structured ASIC Technology
Vendor:
Faraday Technology
Category:
DLL
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process
Input 50M-210MHz, output 50M-210MHz.
Overview
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 40nm | LP | Pre-Silicon |
Specifications
Identity
Part Number
FXDCDL201HH0L
Vendor
Faraday Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
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Frequently asked questions about DLL IP cores
What is Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process?
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process is a DLL IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc Pre-Silicon.
How should engineers evaluate this DLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.