6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an cell design ena…
95 dB of SNR, 24-bit audio CODEC with headphone output and line-out
SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording perform…
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS
Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…
95 dB of SNR, 24-bit stereo audio CODEC with AGC and headphone output
SoC integrators wishing to address portable audio applications like Smart Phones, PMP or Portable Multimedia Devices for mobile c…
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
14-Bit 150MS/s 1.2V/3.3V 250mW ADC, CMOS 130nm
The nSAD_TS130M_3V3_1V2_AD14b150M is a 150MS/s, 13 ENOB, high-precision pipeline AD converter designed on the TSMC 130 M technolo…
Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
The nSAD_TS90GP_1V2_AD2x12b200M is a dual 200MS/s, 11 ENOB, dual pipeline AD converter designed on the TSMC 90 GP technology.
Quad 3.125/6.25 Gbps Backplane SerDes
IP
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
100 dB of SNR, 24-bit stereo audio CODEC with headphone driver and digital mixer
Amidst a rich a-la-carte offering, shCODlp-100.02 is an optimized and configuration around high performance DAC and ADC cores whi…
Single-carrier RF transceiver on TSMC 22nm ULL
Single-carrier RF transceiver on TSMC 22nm ULL
Multi-carrier RF transceiver on TSMC 22nm ULL
Multi-carrier RF transceiver on TSMC 22nm ULL
Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
Integer-N PLL, 800M-3.2G on TSMC 12nm
This present IP is a charge-pump Phase Locked Loop (PLL) circuit, which can cover 800MHz-3200MHz vco output frequency.
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.