Vendor: Aragio Solutions Category: Analog

SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)

The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both sing…

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TSMC 40nm G Silicon Proven View all specifications

Overview

The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both single-ended and differential signaling. This single pad set supports both the DDR2 and DDR3 signaling standards.

Key features

  • • Mode select – DDR2 or DDR3
  • • Single-ended and differential signaling
  • • DDR2 capability
  • o Compliant with JEDEC specification JESD79-2E, DDR2-400
  • o Data transfer rate – up to 400 MHz (800 MT/sec)
  • • DDR3 capability
  • o Compliant with JEDEC specification JESD79-3D, DDR-1333
  • o Data transfer rate – up to 667 MHz (1333 MT/sec)
  • • Staggered CUP wire bond implementation with flip chip option
  • • Power-up sequencing independent design with Power-on Control
  • • Robust ESD Protection
  • o 2KV ESD Human Body Model (HBM)
  • ? Compliant with JEDEC specification JS-001-2012 (April 2012)
  • o 200 V ESD Machine Model (MM)
  • ? Compliant with JEDEC specification JESD22-A115C (November 2010)
  • o 500 V ESD Charge Device Model (CDM)
  • ? Compliant with JESD22-C101E (December 2009)
  • • Latch-up Immunity
  • o Compliant with JESD78D (November 2011)
  • o Tested using I-Test criteria of ±100mA at maximum ambient temperature of +125°C.

What’s Included?

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
TSMC 40nm G Silicon Proven

Specifications

Identity

Part Number
RGO_TSMC28_18V18_HPCP_20C_SSTL_15_18
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Contact Aragio Solutions

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Frequently asked questions about Analog I/O Pad Library IP cores

What is SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)?

SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V) is a Analog IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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