Power On Reset on TSMC CLN12FFC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
- TSMC
- 12nm
- FFC
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Power On Reset on TSMC CLN12FFC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF
The PCIe Gen5 REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN6FF
The PCIe Gen5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3P-CLN3X
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3E
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN2P
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
Multi Rail LDO for SERDES on TSMC CLN3P-CLN3X
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Multi Rail LDO for SERDES on TSMC CLN3E
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Multi Rail LDO for SERDES on TSMC CLN2P
The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
Low Power PLL on TSMC CLN90G-GT-LP
The low-power wide range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
Low Power PLL on TSMC CLN40LP-ULP
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
The Low Power Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock…
Low Power FracN/SSCG PLL on TSMC CLN6FF
The low power Fractional-N SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications n…
Low Power Frac-N on TSMC CLN28HPC+
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN28HPC
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN22ULL
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.