Vendor: Analog Bits Inc. Category: PLL

Low Power PLL on TSMC CLN90G-GT-LP

The low-power wide range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.

TSMC 90nm G View all specifications

Overview

The low-power wide range PLL addresses markets and applications that demand very low power and optimized for area efficiencies. In addition, consumer devices have restrictions on supply voltage due to battery restrictions or board restrictions. The PLLs also needs to be designed on standard digital logic processes and expected to work in noisy SoC environments.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core supply only. The PLL resides inside the IO ring that includes two analog power supply pads, occupying no core area. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The PLL macro fits into any standard IO pad pitch and can be implemented in staggered and in-line IO configurations.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 5 140 MHz Post-Divide Reference Frequency FPFD 5 140 MHz VCO Frequency FVCO 800 MHz Output Frequency FOUT 12.5 400 MHz Output Duty Cycle tDO 45 55 % Total area of macro (excluding bond pad area) A 0.024 sq. mm May vary depending on size of IO slots Chip core area requirement CA 0 sq. mm Total Power IDD 0.8 mA Operational Voltage (Digital) VDIG 1.08 1.2 1.32 V Operational Voltage (Analog) VANA 1.08 1.2 1.32 V Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range

Key features

  • Very low power for consumer and mobile applications – 1uA/VCO-MHz
  • Electrically Programmable PLL for multiple applications
  • Wide Ranges of Input and Output Frequency for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Fully integrated inside customer-specified IO ring
  • Occupies no core area
  • Low power consumption
  • Spread Spectrum tracking capability
  • Uses no external on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection

Block Diagram

Low Power PLL on TSMC CLN90G-GT-LP block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 90nm G —

Specifications

Identity

Part Number
Low Power PLL on TSMC CLN90G-GT-LP
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Analog Bits to Participate in a Customer Test Chip Tapeout on TSMC A14 and Present Papers with Cerebras, Arm and Socionext on Real-Time On-Chip Power Sensing and Delivery at 2026 TSMC Global OIP Ecosystem Events

At TSMC 2026 North America OIP Ecosystem Forum, Analog Bits will showcase new real-time power observability and sensing analog IP in TSMC’s N2P process technology and present a paper with Cerebras; Papers planned with partners at global OIP Ecosystem events to highlight smarter power delivery for scalable SoCs targeting data centers, automotive and more.

Frequently asked questions about PLL IP cores

What is Low Power PLL on TSMC CLN90G-GT-LP?

Low Power PLL on TSMC CLN90G-GT-LP is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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