Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
The (R)GMII library provides the combo driver / receiver and required support cells for (R)GMII signaling.
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexib…
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly…
The SEC28FDSOI18_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver am…
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
Temperature Sensor, +/-3C Accuracy without Trimming - Samsung 8nm
Temperature Sensor, +/-3C Accuracy without Trimming - Samsung 8nm
Samsung 28nm FDSOI MIPI DPHY V1.1
IP
Samsung 28nm FDSOI USB3.0 Type-C PHY
IP
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
IP
Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver
IP
Samsung 28nm FDSOI 1.8v/1.0v APLL
IP
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
LDO, 1.8V to 0.75V, 100mA Output Capability - Samsung 8nm
LDO, 1.8V to 0.75V, 100mA Output Capability - Samsung 8nm