45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ended
16 Gbps APXpress PHY with 4-tap Tx FIR, CTLE, 12-tap DFE, and 30 dB IL target. Part of the Inova APXpress ecosystem
Universal Chiplet Interconnect Express PHY IP - GLOBALFOUNDRIES® 22FDX®
UCIe PHY IP with X16 data width for standard package and up to 8 Gbit/s per pin data rate
Crystal Oscillator for a 32 kHz Crystal - GLOBALFOUNDRIES® 22FDX®
ri_xtalosc_gf22fdx_32k is a crystal oscillator designed to work with 32 kHz crystals.
Voltage and Temperature Sensor - GlobalFoundries® 22FDX®
ri_vtsens_gf22fdx is an integrated (supply-) voltage and temperature sensor IP with integrated ADC and band-gap voltage reference.
A 32Gbps SerDes PHY in GlobalFoundries 22FDX withlow-jitter, half-rate tran mission, and a configurable CTLE-based receiver.
Analog I/O Library with a custom 12V ESD Solution IN GF 55nm
An Analog I/O Library in GlobalFoundries 55nm LPx-BCDlite technology This I/O library is a silicon-proven, flip-chip-optimized an…
Small footprint trusted identity Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
ULP Clock Generator - GLOBALFOUNDRIES 22FDX
ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in energy efficient Systems on Chip.
Standard Cell Libraries GF 55nm
The Standard Cell libraries deliver thousands of optimized cells with each one being optimized for power, area, speed, routing, a…
Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee.
eFPGA on GlobalFoundries GF12LP
All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee.
Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all s…
Auxiliary DAC - 12-bit Successive Approximation Register (SAR) DAC
This digital-to-analog converter implements segmented R-2R and thermometer decoder architecture to achieve 12-bit resolution.
USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
LPDDR4 multiPHY V2 - GF 22FDX18 for Automotive, ASIL B Random, AEC-Q100 Grade 1
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY Plus - GF 12LP18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY Plus - GF 12LP+18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …