Configurable Multi-Channel DMA Controller

The Digital Blocks DB-DMAC-MCn-AHB5 SystemVerilog RTL IP Core is a Scatter-Gather (SG) Direct Memory Access (DMA) Controller for AMBA 5 AHB systems, with a build-time number of independent DMA Channels (1 to 126) and a DMA data path of 8 to 1024 bits. It is the AHB5 member of the DB-DMAC-MC AMBA family, next to the AXI4 and AXI5 controllers.

Each channel runs linked lists of 16-byte descriptor nodes with 32-bit addresses, any byte alignment and up to 16 MB per node, with read and write bursts of 4, 8 or 16 beats or a programmed length. A dedicated AHB5 Read Manager carries the descriptor fetches and source reads, and a dedicated AHB5 Write Manager the destination writes, so reads and writes run concurrently. Measured at 128 bits, two channels use 88.6 % of the bus and one channel 79.6 %.

AHB5 Data Engine

• Two AHB5 Managers: a Read Manager for descriptor fetches and source data and a Write Manager for destination data, running concurrently
• Programmable bursts: INCR4, INCR8 or INCR16 per channel, or a programmed 1 to 256 beats (MCn-MB-AHB5) issued as INCR bursts of up to 16 beats; every burst is clipped at the 1 KB boundary and at the end of the block
• Data FIFO: 32 words of the data width per channel, with a byte rotator between the read and the write side
• Round-robin channel arbitration with an O(log N) parallel-prefix select on each AHB5 Manager; the grant is held for the whole burst; any number of wait states

Descriptor Processing

• Descriptor nodes are fetched over the Read Manager, one burst per 16-byte node (INCR4 at 32 bits, a single beat at 128 bits and wider)
• Per-channel pre-fetch of up to 32 descriptor nodes ahead of execution
• Descriptor list start / branch (DLB), re-start (DLR) and last-node address read-back (DLAR)

Scatter-Gather and Transfer Control

• Linked lists of 16-byte descriptor nodes: 32-bit source, destination and next address, 24-bit byte length (1 byte to 16 MB per descriptor node)
• Chained and ring descriptor structures with the descriptor node's NAV, LDN and WOR flags
• Memory-to-Memory, Memory-to-Peripheral, Peripheral-to-Memory, Peripheral-to-Peripheral
• Unaligned source and destination addresses at any byte, any length (byte rotator; naturally aligned narrow SINGLE transfers for the head and tail of the destination block); no burst crosses a 1 KB boundary
• Fixed-address (FIFO) reads and writes; hardware-paced bursts with per-channel DREQ / DACK pairs for reads and writes
• CPU software or external hardware initiated transfers

Status, Interrupts and Error Handling

• Per-channel status: descriptor list complete and channel done, descriptor read, source read and destination write ERROR responses, data and descriptor parity errors, re-start failure - each with an interrupt mask; a masked error holds the channel until cleared or reset
• Per-channel interrupt outputs; global interrupt status / mask / vector registers (one bank per 32 channels) and one processor interrupt
• Event-safe write-1-to-clear: a hardware event in the same cycle as the clear is never lost
• Optional per-byte parity checking on data and descriptor reads; parity generated on writes
• TrustZone: per-channel HNONSEC and HPROT for each Manager, and a security lock that hides a channel's registers from Non-secure accesses
• Core Identification Register (CIR): vendor, channel count, data width, bus, security and unaligned-addressing flags, revision

Integration

• 1 to 126 channels (one global interrupt bank per 32); data width 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024 bits; 32-bit addressing
• SystemVerilog RTL with a flat-pin top level; AMBA 5 AHB Manager / Subordinate naming
• Elaboration-time checks reject illegal configuration values
• Fully synchronous single clock, rising-edge, no gated clocks, no internal tri-states; technology-independent RTL for ASIC and FPGA
• Sister products for AXI systems: DB-DMAC-MCn-AXI4, DB-DMAC-MCn-AXI4-HT and DB-DMAC-MCn-AXI5 HT

• Memory-to-memory copy engines in AHB5 microcontroller and SoC subsystems
• Scatter-gather DMA for networking, storage and sensor data movement
• Peripheral data streaming with hardware request / acknowledge pacing
• Offload of bulk memory copies from the CPU, under Linux or bare metal

• RTL: Synthesizable SystemVerilog (IEEE 1800-2012) with a flat-pin top level; or a technology-specific netlist for FPGAs
• Constraints / filelists: Synopsys Design Constraints, compile-ordered filelist, lint script and waivers
• Test bench: Self-checking directed and generic suites, AHB5 memory models, AHB5 protocol assertions, regression driver with expected results and coverage scripts
• Models: C++ cycle model build
• Software: Bare-metal C driver with reference program; Linux platform driver, UAPI header and device-tree example
• Documents: Data sheet, Technical Reference Manual, IP Integration Guide, IP-XACT component descriptor, coverage report, test matrix, regression evidence