Vendor: Eliyan Category: Custom

Die-to-Memory (D2M) PHY

Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutio…

Overview

Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutions.

Block Diagram

Applications

  • Chiplets connected on standard organic packages without large silicon interposers or silicon bridges but with interposer-like bandwidth/power/latency.
  • SiP applications that benefit from up to at least four times the substrate area compared to the largest silicon interposer and thus a far higher number of chiplets in the package, resulting in major performance and power advantages.
  • ASIC designs where a Network on Chip is split across two or more chiplets.
  • Applications that benefit from placement flexibility to mix and match chiplets of different dimensions.
  • Chiplet applications–such as HBM—where there must be physical separation between a hot ASIC and heat-sensitive dies.

Specifications

Identity

Part Number
UMI
Vendor
Eliyan
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Custom IP core

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation.

RISC-V basics: The truth about custom extensions

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), edge computing, automotive, and industrial markets continue to expand, they are driving a fundamental shift in processor design.

Frequently asked questions about Custom Die-to-Die IP cores

What is Die-to-Memory (D2M) PHY?

Die-to-Memory (D2M) PHY is a Custom IP core from Eliyan listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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