Vendor:
Eliyan
Category:
Custom
IP core products for Die-to-Die and Chip-to-Chip connections
The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…
Overview
Eliyan uses NuLink technology to deliver low-power and high-performance die-to-die (D2D) IP core products to connect ASICs on the same package substrate. Eliyan uses NuLink-XS technology to deliver low-power and high-performance chip-to-chip (C2C) IP core products. Our PHY IP core products support multiple industry standards and are available on both standard packaging and advanced packaging.
For Standard Packaging D2D connections
Eliyan has a family of NuLink-SP high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same standard organic/laminate package substrate. Eliyan’s PHY technologies with patented implementation techniques enable the same levels of performance and power as those provided by advanced packaging options. They provide benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry standard packaging. In many applications this eliminates the need for advanced packaging technologies such as silicon interposers or silicon bridges.
The NuLink PHY IP cores for standard packaging are designed for standard organic/laminate packages with bump pitches from 100um to 130um. Eliyan offers NuLink PHY IP products for industry standards (including UCIe and BoW) as well as unique value-added products including UMI™ and SBD. The NuLink PHY IP cores typically have 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD).
| Eliyan D2D Std Pkg |
NuLink UCIe Unidirectional |
NuLink UCIe Unidirectional 64Gbps |
NuLink BoW Unidirectional 64Gbps |
NuLink SBD Simultaneous Bidirectional |
Units |
|---|---|---|---|---|---|
| Process Node | 5nm/3nm/2nm | 3nm/2nm | 3nm/2nm | 3nm/2nm | |
| # Data Lanes | 32 Tx + 32 Rx | 32 Tx + 32 Rx | 32 Tx + 32 Rx | 64 Tx + 64 Rx | |
| Data Rate/Lane | 32 | 64 | 64 | 64 (2x32) | Gbps |
| Beachfront BW Metric | 1.8 | 3.6 | 4.1 | 4.1 | Tbps/mm |
| Area BW Metric | 1.1 | 2.3 | 3.1 | 3.1 | Tbps/mm2 |
| Reach | 50 | 50 | 50 | 5 | mm |
For Advanced Packaging D2D connections
Eliyan has a family of NuLink-AP extremely high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same advanced package silicon interposer or via silicon bridges. Eliyan’s PHY technologies with patented implementation techniques enable improved performance and power over other solutions on advanced packaging, in order to meet the performance requirements of today’s most demanding HPC/AI applications.
The NuLink-AP PHY IP cores for advanced packaging are designed for silicon interposers and bridges with bump pitches from 40um to 55um. Eliyan offers NuLink PHY IP products for industry standards (including UCIe) as well as unique value-added products including UMI™ and SBD. The NuLink PHY IP cores typically have 128 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, UMI, SBD).
| Eliyan D2D Adv Pkg |
NuLink UCIe Unidirectional |
NuLink SBD Simultaneous Bidirectional |
Units |
|---|---|---|---|
| Process Node | 4nm/3nm/2nm | 3nm/2nm | |
| # Data Lanes | 64 Tx + 64 Rx | 128 Tx + 128 Rx | |
| Data Rate/Lane | 40 | 64 (2x32) | Gbps |
| Beachfront BW Metric | 13.2 | 21.1 | Tbps/mm |
| Area BW Metric | 9.1 | 14.6 | Tbps/mm2 |
| Reach | 2 | 2 | mm |
For Chip-to-Chip connections (between packaged devices)
Eliyan has an industry-first family of NuLink-XS chip-to-chip (C2C) IP core products designed to be integrated into ASIC designs to connect two chips on separate packages across a PCB. Eliyan’s PHY technologies with patented implementation techniques enable much lower power at the same levels of performance as SerDes connections, while providing benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry-standard packaging.
The NuLink-XS chip-to-chip (C2C) PHY IP cores enable longer-reach C2C (vs. D2D) connections between two packaged devices on the same PCB with much lower power than 112G/224G SerDes solutions.
| Eliyan C2C Std Pkg |
NuLink-XS 1.0 long-reach C2C |
NuLink-XS 2.0 long-reach C2C |
Units |
|---|---|---|---|
| Process Node | 3nm/2nm | 3nm/2nm | |
| # Data Lanes | 16 Tx + 16 Rx | 16 Tx + 16 Rx | |
| Data Rate/Lane | 32 - 40 | 64 | Gbps |
| Silicon Beachfront BW Metric | 1.0 - 1.3 | 2.0 | Tbps/mm |
| Area BW Metric | 0.75 - 0.94 | 1.5 | Tbps/mm2 |
| Reach | 100mm | 100mm | mm |
Block Diagram
NuLink-SP D2D PHY for Std Pkg @ 110um bump pitch
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Specifications
Identity
Part Number
NuLink™ IP
Vendor
Eliyan
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Custom Die-to-Die IP cores
What is IP core products for Die-to-Die and Chip-to-Chip connections?
IP core products for Die-to-Die and Chip-to-Chip connections is a Custom IP core from Eliyan listed on Semi IP Hub.
How should engineers evaluate this Custom?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.