OPENEDGES Technology, Inc. IP Cores

The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.

• UCIe
• Available on request
• UCIe 1.1

The inference neural processing unit (NPU) IP is suitable for high-performance edge devices including automotive, cameras, and mo…

• NPU
• Now

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Samsung
• 5nm
• SF5

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Samsung
• 14nm
• Silicon Proven

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Controller + PHY + 1
• LPDDR4

Features a mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environm…

• Controller + PHY + 1

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Controller + PHY + 1
• LPDDR5 + 1

Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…

• NPU
• Production-and market-proven
• Now

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Controller + PHY + 1
• LPDDR5

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Controller + PHY + 1

Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduli…

• Controller

The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end i…

• Network-On-Chip
• Silicon Proven & Market Proven
• Now

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integrati…

• LPDDR
• Silicon proven
• Now
• JEDEC, JESD209-5C, JESD209-…

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integrati…

• LPDDR
• Silicon proven
• Now
• JEDEC, JESD209-5C, JESD209-…

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integrati…

• LPDDR
• Silicon proven
• Now
• JEDEC, JESD209-5B, JESD209-…