UCIe Die-to-Die Chiplet Controller
The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.
- UCIe
- Available on request
- UCIe 1.1
OPENEDGES is an IP technology provider for Smart Computing enabling Internet of Smart Things. OPENEDGES delivers IPs in two key technology areas in Smart Computing; 1) Artificial Intelligence (Deep Learning) Accelerator and 2) Memory Subsystem IP.
For Memory Subsystem, we provide Memory Controller IP (OMC), LPDDR5x/5/4 PHY & High speed Network on-chip interconnect IP (OIC). OPENEDGES is the only IP company providing DDR controller, DDR PHY IP & High speed NoC bus interconnect IP all together. When used together within an SoC, OMC, OPHY and OIC provide significant synergy of higher performance, reduced SoC design efforts and a lot easier post-silicon debugging/tuning. And our Artificial Intelligence Accelerator (ENLIGHT) features higher compute density & low-power consumption through our unique bit-precision optimization technology.
ENLIGHT and our Memory system IP gives synergy of high efficiency for performance demanding Artificial Intelligence acceleration task. Our IPs are silicon proven and market proven with many Tier 1 semiconductor companies.
UCIe Die-to-Die Chiplet Controller
The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.
Highly scalable inference NPU IP for next-gen AI applications
ENLIGHT Pro is a high-performance, scalable NPU IP designed for edge AI applications, including automotive and cameras.
4-/8-bit mixed-precision NPU IP
Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…
OPENEDGES On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end i…
4/8-bit mixed-precision NPU IP
Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…
Features a mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environm…
Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduli…
The memory subsystem of the new generation of AI chips needs to have numerous features, such as the ability to reduce latency, co…