Deep learning accelerator
High performance-efficient edge deep learning accelerator for small LLM/VLM/VLA and CNN/RNN/LSTM
Overview
AndesAIRE® AnDLA® I370 is a deep learning accelerator (DLA) designed for high-performance, cost-sensitive edge and endpoint AI inference. It supports popular AI framework formats (TensorFlow Lite, PyTorch, ONNX), NN models (CNN/RNN/ViT/SLM) and datatype INT8/INT16.
AndesAIRE® AnDLA® I370 performs a wide range of neural network operations—convolution, fully connected, elementwise, activation, pooling, channel padding, upsampling, and concatenation—and leverages internal DMA and local memory to maximize hardware efficiency. Operator and layer fusion further improve execution efficiency.
Key configurable parameters of AndesAIRE® AnDLA® I370 include MAC count, local memory size, Programmable Tensor Operator Set Architecture, and DSU (divide/square), delivering flexible computing power up to 4 TOPS at 1 GHz for diverse applications.
Key features
- Configurable MACs: 32, 64, 128, 256, 512, 1024, 2048 (INT8)
- Maximum performance up to 4 TOPS at 1GHz
- Data type: i8i8, i8i16, i16i16 (weight INT16, feature map INT16)
- Configurable local memory: 16KB to 4MB
- Multi-dimensional Direct Memory Access (DMA)
- Bus interfaces: AHB-64b, AXI-64/128/256/512b
- Neural network (NN) models:
- Image and Video: MobileNet-v1/v2/v3, ResNet-8/50, Tiny
YOLO v1/v2/v7, YOLO v3/v5/v8s, Inception-v2, EfficientNet-
Lite, MobileNet-v1-SSD, BlazeFace, MCUNet-VWW2,
GhostFaceNet, SqueezeNet v1.1, ShuffleNet-v2, PUNET, … - Speech/Voice and Audio: RNNoise, DS-CNN, Tiny
Wav2letter, DTLN, BC-ResNet-8, U-Net, DeepFilterNet, … - ViT/SLM: MobileViT, Swin Transformer, BertTiny, YOLOv12,
TinyLlama 2 110M
- Image and Video: MobileNet-v1/v2/v3, ResNet-8/50, Tiny
- Operators: MatMul, MHA, FeedForward, Conv2D, Depthwise
Conv, Pointwise Conv, Transpose Conv, Dilated Conv,
Elementwise (Add, Add_const, Sub, Sub_const, Mult, Mult_const,
input vector broadcasting to tensor), Fully Connected, Activation
(Hardsigmoid, Hardswish, leaky ReLU, ReLU, ReLU6,
ReLU_n1_to_1, MISH, Softplus, Logistic, Swish, Tanh, SiLU,
GeLU, PReLU), Pooling (Average, Global Avg, Max), Upsampling,
Concatenation, Split, Strided slice, D2S, S2D, SpaceToBatchND,
BatchToSpaceND, Reshape, Transpose, Batch norm, Channel
padding, GRU, LSTM, RNN, Tiny channel - Programmable Tensor Operator Set Architecture (configurable)
- Sqrt, div (configurable)
- Operator and layer fusion
Block Diagram
Applications
- AIoT and TinyML on edges and endpoints
- Smart cameras
- Smart sensors
- Sensor hubs
- Wearables
- TWS earbuds
- Hearing aids
- Smart home appliances
- Smart cockpit
- Robotics
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Andes' Deep learning accelerator IP core
Frequently asked questions about Edge AI Accelerator IP cores
What is Deep learning accelerator?
Deep learning accelerator is a Edge AI Accelerator IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this Edge AI Accelerator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Edge AI Accelerator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.