IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
- IBM
- 65nm
- LPe
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
IBM 65nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
This IP is a programmable Analog PLL suitable for high speed clock generation.
IBM10SF 1.0v/2.5v APLL Brief Specification
This IP is a programmable Analog PLL suitable for high speed clock generation.
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
The VT18PLL500 is a macro cell for clock generation.
SMIC 0.18um Stereo Speaker Drivers
The SMIC18_SPKDRIVER_01 specifies the design of stereo speaker drivers.
SMIC 0.18¦Ìm 5v-3.3v/1.8v Power Regulator
Based on SMIC 0.18¦Ìm 3.3v/1.8v Logic process, this design of Power Regulator is to provide both 3.3v and 1.8v power supplies whi…
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 0.18um 12-Bit 8 Input 1M/200k SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SMIC 0.13um 3.3V Power On Reset
Present Power on Reset generates system reset pulses (POR33) when the 3.3V power supplier (VIN33) is turned on.
The present IP is a Power On Reset (POR) circuit without any external resistor or capacitor.
SMIC 0.13um 3.3v/1.2v Power Regulator
Present IP devises a NO-CAP regulator which generates 1.2V voltage from 3.3V power supply and provides100mA plus loading current.
This IP is a programmable Analog PLL suitable for generating system clock.
SMIC 0.13um 1.2v/3.3v PLL Specification
This PLL is designed for audio clock generation.
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
UMC 0.18um 1.8v 60MHz Ring Oscillator
The present IP is a Ring Oscillator which is controlled by the external 1.2v bandgap reference.
Power-on reset circuit for 1.8V and 3.3V - TowerJazz 0.18um
Power-on reset circuit monitoring both 1.8V and 3.3V supplies and with extended reset duration.
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, this IP integrates five sub-modules: 1.8~3.3v(1.62~3.6V) to 1.2v Regulator, 200M…