Overview
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, this IP integrates five sub-modules: 1.8~3.3v(1.62~3.6V) to 1.2v Regulator, 200MHz Ring Oscillator and three POR (Power On Reset) cores to detect 3.3v, 1.8v or 1.2v input separately. The Regulator is to provide 1.2v power supply which is regulated from the single 3.3v supply and the 3.3v supply input can drop to 1.62v minimum. The maximum output current is 100mA. The Ring Oscillator is to output 200MHz stable clock without any external components. The reference control voltage is from the prior Regulator. The output frequency can be fairly accurate (±10%) by trimming the resistance in case of any process variations. With the 0.6v bandgap reference voltage from the Regulator, the three PORs can each detect one of three different voltage inputs: 3.3v, 1.8v or 1.2v separately, and output a flag when detected voltage reaches the trigger point. This particular physical IP has the scaled up version of S13V33_MMC_05C which is designed to be used in foundry’s 0.11um (90% shrink) process.
Learn more about Mixed Signal Subsystem IP core
Increasingly, product managers are considering a custom Analog SoC as an effective way to drastically reduce BOM costs. What would have been considered a radical product innovation just a few years ago, is now viewed as a viable route as even where product volumes are considered low NRE costs can in fact be recovered in short period of time. Innovative SoC solutions are challenging but the benefits are compelling where risk can be mitigated by choosing a development partner with a clear understanding of all the system components and of the various technology options for the SoC implementation. In a recently issued paper, S3 Group’s experts talk about the advantages of custom SoCs and build a strong business case for investment in a SoC development.
This paper describes the design & verification methodology used on a recent large mixed signal System on a Chip (SoCs) which contained radio frequency (RF), analog, mixed-signal and digital blocks on one chip. We combine a top-down functional approach, based on early system-level modelling, with a bottom-up performance approach based on transistor level simulations, in an agile development methodology. We look at how real valued modelling, using the Verilog-AMS wire that carries a real value (wreal) data type, achieves shorter simulation times in large SoCs with high frequency RF sections, low bandwidth analogue base-band sections and appreciable digital functionality including filtering and calibration blocks.
This paper discusses verification process of a mixed signal core of an HSIC PHY. After explaining the specific topic related with HSIC comparison to USB, the verification strategy is shown. The strategy is explained from the top level point of view, and detailed description is covered in subsequent sections. In following sections the system level testbench and interoperability testbenches are explained parallel to local testbenches for analog block characterization.
Don Dingee
This article suggests an innovative approach to build an optimal PMNet per application requirements, based on the definition of four standardized voltage levels (further defined as Interfaces for the Distribution of Power). Finally, it demonstrates the advantages of this approach from which regulator suppliers or designers, SoC integrators and system makers can benefit.
Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).
