Overview
This IP is a programmable Analog PLL suitable for generating system clock. It contains a PFD, Charge pump, 3rd order loop filter, a 1-64 input clock divider, a 1-128 feedback clock divider, a 1-8 output clock divider and VCO. High speed VCO can run from 200MHz to 500MHz. By setting DM [5:0], DN [6:0] and DP[2:0] to different values according to different REFIN value, CLK and CLKO will be locked at the multiples of the input frequency.
Learn more about PLL IP core
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