SMIC 0.13um 1.8V Power On Reset
Present Power on Reset generates system reset signal (POR18) when 1.8V power supplier (VIN18) is turned on.
- SMIC
- 130nm
- G
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
SMIC 0.13um 1.8V Power On Reset
Present Power on Reset generates system reset signal (POR18) when 1.8V power supplier (VIN18) is turned on.
SMIC 0.13um 1.2V Power On Reset
Present Power on Reset generates system reset signal (POR12) when 1.2V power supplier (VIN12) is turned on.
SMIC 0.13um 1.2V Power On Reset
Present Power on Reset generates system reset pulses (POR12) when 1.2V power supplier (VIN12) is turned on.
SMIC 0.13um 3.3V/1.2V Power on Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.2V power suppliers are turned on.
SMIC 0.13μm 1.62~3.3v->1.2v Power Regulator
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…
SMIC 0.13μm 1.62~3.3v->1.2v Power Regulator
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for generating system clock.
This PLL is designed for audio clock generation.
SMIC 0.13um 1Channel 10Bit 10MHz DAC
S13V33_R2RDAC_01 is a 10bit@10MHz DAC IP which implements a 7-bit (from D [0] to D [6]) R2R_Ladder and 3-bit thermometer decoder …
IBM 65nm 24-bit Stereo Sigma-Delta ADC
The I65GV25_ADC_01 specifies the design of a high-performance 24-bit stereo Audio ADC for portable digital audio systems.
IBM 65nm 24bit Sigma-Delta DAC
The I65GV25_DAC_01 specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems.
This PLL is designed for audio clock generation.
This analog 2-1 MUX is designed for low speed application.
IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
IBM 65nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
This IP is a programmable Analog PLL suitable for high speed clock generation.
IBM10SF 1.0v/2.5v APLL Brief Specification
This IP is a programmable Analog PLL suitable for high speed clock generation.
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
The VT18PLL500 is a macro cell for clock generation.