Overview
This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports 256*fs clock output and 384*fs clock output, where fs is the audio system sample rate of 32kHz/44.1kHz/48kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.
Learn more about PLL IP core
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