The sCOD100-uLP-ANC-H1-LR-D.02 is a mixed (analog and digital) Virtual Component containing a stereo ADC, a stereo DAC with headp…
- TSMC
- 40nm
- ULP eFlash
- Pre-Silicon
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
The sCOD100-uLP-ANC-H1-LR-D.02 is a mixed (analog and digital) Virtual Component containing a stereo ADC, a stereo DAC with headp…
Always-on Voice Activity Detection interfacing with analog microphones
The WT-a-HD.01 is a mixed analog/digital Virtual Component (ViC) containing a Voice Activity Detection (VAD) engine for ultra low…
24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
The sADC-uLP-ANC.04 is a mixed (analog and digital) Virtual Component containing three mono ADCs, and additional functions offeri…
Dual band 2.4GHz WiFi ah + 15.4g RF Transceiver IP
It is a fully integrated dual-band transceiver IP for 802.15.4g and 802.11ah applications.
Adaptive Body Bias Generator - GLOBALFOUNDRIES 22FDX
RI_ABB_GF22FDX is a cutting-edge adaptive body bias (ABB) generator for GLOBALFOUNDRIES® 22FDX® technology.
Ultra-Low Power Fractional PLL IP in in TSMC (12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
Low Power Fractional PLL is a general purpose frequency synthesizer with an input reference frequency range from 10 to 240 MHz an…
Low Power Fractional PLL IP in TSMC(12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
M31 LPFPLL is a low-power programmable fractional-N (LPF), phase-locked loop (PLL) for frequency synthesis.
3.3V 100MHz Oscillator IO Inline Pad Set
The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell.
3.3V 100MHz Oscillator IO Staggered Pad Set
The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell.
3.3V 32kHz Oscillator IO Inline Pad Set
The 3.3V 32kHz Oscillators library provides a 32kHz real time clock oscillator macro I/O cell.
3.3V 32kHz Oscillator IO Staggered Pad Set
The 3.3V 32kHz Oscillators library provides a 32kHz real time clock oscillator macro I/O cell.
Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges.
TSMC CLN28HPC 12-bit 250MHz Current Steering DAC [2ch]
The IGADACT10A is a general-purpose 2-channel digital to analog converter with 12-bits resolution.
TSMC CLN28HPC+ 2.4GSps Analog Front-End
The IGAAFET05A which contains ADCs, DACs and PLLs is an analog front-end (AFE) IP for RF applications.
Low Power PLL for TSMC 40nm ULP
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is design…
Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter - GlobalFoundries 55nm
CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Re…
TS-4x8 V-Band Array Antenna 4x8 Array Antenna, 57 – 67 GHz V-Connector 1.85 mm
The TS-4x8 V-Band Array Antenna is a 57 to 67 GHz planar antenna with a bore-sight gain of min.
The RAR-eSR-qLR Retention Alternating Regulator combines two regulation sub-components: a high-efficiency switching regulator (eS…
RAR-eSR-qLR-ref-[1.62-3.63]-[0.55-2.5].04, as any Power Management Virtual Component designed by Dolphin Design, is readily retar…
The RAR-eSR-qLR Retention Alternating Regulator combines two regulation sub-components: a high-efficiency switching regulator (eS…