Vendor: CoreHW Category: PLL

Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter - GlobalFoundries 55nm

CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Re…

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GlobalFoundries 55nm Silicon Proven View all specifications

Overview

CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Rel11 and Rel12. CorePLL frequency synthesis sub-system enables single transceiver LTE CA. CorePLL consists of two fully integrated PLLs with integrated VCOs and loop filters. CorePLL is versatile frequency synthesizer so lution with small size, high-performance and ultra low-power. Power consumption is only 18mA from 1.35V supply (24mW). CorePLL supports variety of different systems and ref erence clock frequencies. CorePLL is imple mented using standard 55nm CMOS process. CorePLL is available in QFN 6x6mm package. PLL1 and PLL2 synthesizers are also available as IPs.

Key features

  • PLL1 for LTE with VCO1
  • PLL2 for LTE&GSM with VCO1 and VCO2
  • Small size, high-performance and low-power (24mW)
  • Various power and performance modes
  • Power supply 1.35V and 1.8V
  • Reference signal (FREF) from 10MHz to 400MHz
  • Programmable reference divider (/1, /2, /4 & /8)
  • Output RF signal (FOUT) from 1.333GHz up to 8GHz
  • IQ Dividers (/2 & /4) for RX&TX down-to 333MHz
  • Integrated loop filter with adjustable loop response
  • Integrated bandgap reference and LDOs
  • SPI control bus (IO) and test IO
  • Digital calibrations and lock detection
  • Fast settling <100 μs

Block Diagram

CorePLLCAGF55 block diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 55nm 55 550 nm Silicon Proven

Specifications

Identity

Part Number
CorePLLCAGF55
Vendor
CoreHW
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

CoreHW
HQ: Finland
Contact CoreHW

Learn more about PLL IP core

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Semiconductor IP sales have changed dramatically over the past two decades. The volume has increased, and in the digital sector, processes have become refined and structured. Yet, analog IP remains a fundamentally more challenging and less standardized area, one where best practices are still evolving and where both buyers and sellers face significant hurdles.

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about PLL IP cores

What is Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter - GlobalFoundries 55nm?

Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter - GlobalFoundries 55nm is a PLL IP core from CoreHW listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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