Aragio Solutions Achieves ISO 9001:2015 Certification
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Vendor:
Aragio Solutions
Category:
Oscillator
3.3V 32kHz Oscillator IO Staggered Pad Set
The 3.3V 32kHz Oscillators library provides a 32kHz real time clock oscillator macro I/O cell.
Overview
The 3.3V 32kHz Oscillators library provides a 32kHz real time clock oscillator macro I/O cell. An adapter cell is included to utilize this oscillator with libraries based on the 1.8V pad ring bus structure.
These 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 3.3V Support: Power. That library contains the DVDD/DVSS power cells necessary for ESD protection, the POC and VREF cells, and a rail splitter to isolate the oscillator in its own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
These 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 3.3V Support: Power. That library contains the DVDD/DVSS power cells necessary for ESD protection, the POC and VREF cells, and a rail splitter to isolate the oscillator in its own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key features
- 32 KHz RTC Oscillator Features
- ? Designed to use a 32.786 kHz external crystal for Real Time Clock applications.
- ? Optimized for low power, stability and minimum jitter
- ? Characterized with crystal loading capacitors ranging from 4 pF to 35 pF.
- ? Speed-up circuitry for fast startup
- ? Power-down mode
- ? Operates on core power only (VDD/VSS cells embedded)
What’s Included?
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 22nm | 22 220 nm | Silicon Proven |
Specifications
Identity
Part Number
RGO_GF22_18V33_FDX_25C_OSC_032
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Learn more about Oscillator IP core
Aragio Solutions Offers Suite of Programmable GPIO I/O Libraries Supporting 65nm Common Platform Technology Available for Chartered Customers
ARAGIO announced today the immediate availability of silicon-proven I/O libraries for the 65-nanometer (nm) Common Platform technology process available from Chartered Semiconductor Manufacturing Ltd.
Aragio Solutions Offers Suite of High-Performance Mixed-Signal IP and I/O Libraries Targeted to Advanced Processes from Chartered
Critical IP Components Available on Chartered’s Leading-Edge Manufacturing Platform
Frequently asked questions about Oscillator IP cores
What is 3.3V 32kHz Oscillator IO Staggered Pad Set?
3.3V 32kHz Oscillator IO Staggered Pad Set is a Oscillator IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
How should engineers evaluate this Oscillator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Oscillator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.