Low noise PLL operating at up to 3.25GHz (40nm TSMC)
PSI3GLP_T4 is a low jitter PLL operating from 2GHz to 3.3GHz continuously, and with the output divider it can cover 1/2 and 1/4 s…
- TSMC
- 40nm
- G
PLL IP cores (Phase-Locked Loop IP) are essential components in modern SoC, ASIC, and mixed-signal designs, enabling precise clock generation, frequency synthesis, and jitter reduction.
Phase-locked loop IP is widely used in applications such as high-speed interfaces (SerDes, PCIe, Ethernet), wireless communication, processors, and clock distribution networks.
This page allows you to compare PLL IP cores from leading vendors by frequency range, jitter performance, power consumption, process node compatibility, and supported use cases.
Whether you need a low-power PLL for IoT or a high-performance low-jitter PLL for high-speed data links, you can quickly identify the most suitable solution for your design.
Low noise PLL operating at up to 3.25GHz (40nm TSMC)
PSI3GLP_T4 is a low jitter PLL operating from 2GHz to 3.3GHz continuously, and with the output divider it can cover 1/2 and 1/4 s…
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control …
SMIC 65nm 1.2v/2.5v Spread Spectrum PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control …
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 0.13um 1.2v / 3.3v Audio PLL
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
Mixed-Mode Clock Manager (MMCM) Module
The MMCM primitive in Virtex®-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a giv…
SMIC 0.18um 1.8v APLL with Free Running
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for generating system clock.
This PLL is designed for audio clock generation.
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
IBM10SF 1.0v/2.5v APLL Brief Specification
This IP is a programmable Analog PLL suitable for high speed clock generation.
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
The VT18PLL500 is a macro cell for clock generation.