Overview
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 200MHz to 500MHz. It contains a 1-64 input clock divider (DM), a 1-128 feedback clock divider (DN), a 1-8 output clock divider (DP) and a fraction control block (FRAC). It can work either in Integer Mode or in Fraction Mode. By setting DM, DN, DP and FRAC to different values, the output clock will be locked at different multiples of the input frequency. A lock indicator is also included in this PLL. Its output shows whether the output clock is at the right multiples of the input clock.
Learn more about PLL IP core
How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.
Jian Yang, Sween Kang (Synopsys)
This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.
This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
