Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: PLL

IBM 10SF 65nm 2.5v PLL

This PLL is designed for audio clock generation.

Overview

This PLL is designed for audio clock generation. The reference clock is 12MHz, 13.5MHz or 19.2MHz, which can be either from crystal OSC or from internal clock source. It supports 256*fs and 128*fs clock output, where fs is the audio system sample rate of 8k/11k/12k/16k/22k/24k/32kHz/44.1kHz/48kHz/192k. The IP integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.

Key features

  • Process: IBM 10SF 65nm CMOS process
  • Supply voltage: 2.5v +/-10%
  • Reference input: 12MHz, 13.5MHz or 19.2MHz
  • Clock output: 24.572MHz, 12.286MHz, 11.294MHz, 8.190MHz,6.143MHz, 5.647MHz, 4.095MHz, 3.071MHz, 2.823MHz, 2.048MHz
  • Output duty cycle: 30~70%
  • Current: <3mA
  • Operating temperature: -40~125°C

Silicon Options

Foundry Node Process Maturity
IBM 65nm LPe

Specifications

Identity

Part Number
I65GV25_PLL_05
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Frequently asked questions about PLL IP cores

What is IBM 10SF 65nm 2.5v PLL?

IBM 10SF 65nm 2.5v PLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for ibm.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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