Learn more about Monitoring IP core
In this work, the authors propose a centralized performance monitoring architecture to efficiently collect, correlate, and process architectural events across multiple hardware components. Their design introduces Event Monitoring Units (EVUs) that capture and forward microarchitectural events to an Advanced Performance Monitoring Unit (APMU).
Discover why scaling modern SoCs requires more than just sensors. Learn how the proteanTecs hardware monitoring system uses a unified infrastructure to connect
In the modern Systems-on-Chip (SoC), the Ad vanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent counter- measures lack a dedicated real-time protocol semantic analysis and evade protocol compliance checks. This paper tackles this AXI vulnerability issue and presents an intelligent hardware monitoring system (IMS) for real-time detection of AXI protocol violations.
What happens to critical power-related considerations when the same chip is handled two different ways, with or without visibility from within? This article begins by examining how the absence of on-chip monitoring impacts peak power, average power, and Di/Dt noise (rate of current change), as illustrated in the diagram below and the subsequent discussion. It then details how these aspects change when in-chip telemetry is available.
The authors propose a holistic approach to monitor energy consumption at runtime without the need of running complex (micro-)architectural models. Their approach is based on a measurement board coupled with a FPGA-based System-on-Module.
Unfortunately, precise thermal monitoring reached an inflection point at 2nm, with traditional solutions proving less practical below 3nm. To tackle the issue, this article delves into a novel approach, accurate to ±1.0°C, that overcomes this critical challenge.
