Vendor: Siemens Tessent Embedded Analytics Category: Monitoring

Tessent in-life monitoring

The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC.

Overview

The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC. Embedded software based on the Tessent Embedded SDK can drive the Tessent Embedded Analytics smart monitors to create a self-contained on-chip monitoring system.

Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, data can be continuously collected and analyzed on chip, before results and key data points are exported and analyzed centrally. The Tessent Embedded Analytics instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces.

Key features

  • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
  • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
  • Status Monitors provides embedded logic analyzer capability
  • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
  • Static instrumentation provides a nonintrusive mechanism for conde instrumentation.
  • Direct Memory Access (DMA) analytic module provide direct memory access to system memory from debug host.

Benefits

  • Observe if your SoC behaves as it was meant to
  • Enable continuous monitoring and fleet analytics
  • Root-cause performance degradations and memory corruption

What’s Included?

  • Parameterized soft core (Verilog RTL)
  • Available UVM verification IP
  • Tessent Embedded SDK software development kit

Specifications

Identity

Part Number
Tessent in-life monitoring
Vendor
Siemens Tessent Embedded Analytics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Monitoring IP core

Debugging complex RISC-V processors

To debug and profile a RISC-V processor that comprises tens or hundreds of cores and processes billions of instructions each second can be challenging. Is the software running as expected? Does the verification team see the same behavior as the firmware engineers or application developers?

Frequently asked questions about system monitoring IP cores

What is Tessent in-life monitoring?

Tessent in-life monitoring is a Monitoring IP core from Siemens Tessent Embedded Analytics listed on Semi IP Hub.

How should engineers evaluate this Monitoring?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Monitoring IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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