Overview
The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC. Embedded software based on the Tessent Embedded SDK can drive the Tessent Embedded Analytics smart monitors to create a self-contained on-chip monitoring system.
Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, data can be continuously collected and analyzed on chip, before results and key data points are exported and analyzed centrally. The Tessent Embedded Analytics instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces.
Learn more about Monitoring IP core
Discover why scaling modern SoCs requires more than just sensors. Learn how the proteanTecs hardware monitoring system uses a unified infrastructure to connect
In the modern Systems-on-Chip (SoC), the Ad vanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent counter- measures lack a dedicated real-time protocol semantic analysis and evade protocol compliance checks. This paper tackles this AXI vulnerability issue and presents an intelligent hardware monitoring system (IMS) for real-time detection of AXI protocol violations.
What happens to critical power-related considerations when the same chip is handled two different ways, with or without visibility from within? This article begins by examining how the absence of on-chip monitoring impacts peak power, average power, and Di/Dt noise (rate of current change), as illustrated in the diagram below and the subsequent discussion. It then details how these aspects change when in-chip telemetry is available.
The authors propose a holistic approach to monitor energy consumption at runtime without the need of running complex (micro-)architectural models. Their approach is based on a measurement board coupled with a FPGA-based System-on-Module.
Unfortunately, precise thermal monitoring reached an inflection point at 2nm, with traditional solutions proving less practical below 3nm. To tackle the issue, this article delves into a novel approach, accurate to ±1.0°C, that overcomes this critical challenge.
Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events.