SLM Clock & Delay Monitor IP

Measure delay between edges of a signal(s)

The SLM Clock & Delay Monitor (CDM) IP can be implemented in silicon with minimal area overhead. It doesn’t need any accurate high speed reference clock and provides accurate time delay measurement. It can be used for measuring clock duty cycle, memory access time, delay line characteristics, etc. It has IEEE 1500/1687 interface for connecting to test fabric. The SLM CDM IP is also available as an ISO 26262 ASIL-B ready product.

Highlights

• Accurate delay measurement between two edges
• No high-speed high accuracy reference clock required
• Low overhead for data processing
• Small form factor
• EDA integration for automated insertion and connection
• Capture state of silicon precisely at any stage of its lifecycle
• Accuracy is not affected by ageing

SLM Functional Monitors

Functional monitors are key to the success of Silicon Lifecycle Management (SLM). These monitors are embedded in the silicon and report out health of critical functions of the chip. Data from functional monitors can be collected at any stage of silicon lifecycle and analyzed to gather insights. Based on these insights actions can be taken to improve performance or mitigate an operational issue. Memory, CPU workload, interface, clock, delay, etc. are some critical functions on a SOC worth monitoring. Synopsys’ functional monitors are enabled with EDA and software automation for ease of use.

• No high-speed high accuracy reference clock required
• Small footprint
• Available as soft IP with flexibility to customize

• Clock duty cycle quality check
• Memory access time tracking with BIST
• Digital delay line test characterization
• Optimize silicon performance for safety critical applications

• Clock insertion delay
• Clock duty cycle
• Memory access time (Tcq)
• Delay line characteristic
• Ring oscillator frequency