Why Hardware Monitoring Needs Infrastructure, Not Just Sensors
Discover why scaling modern SoCs requires more than just sensors. Learn how the proteanTecs hardware monitoring system uses a unified infrastructure to connect
Vendor:
Siemens Tessent Embedded Analytics
Category:
Monitoring
Tessent Bus Monitor
The Tessent Embedded Analytics Bus Monitor provides non-intrusive monitoring of interconnect activity across all major standards,…
Overview
The Tessent Embedded Analytics Bus Monitor provides non-intrusive monitoring of interconnect activity across all major standards, including Arm® AMBA® AXI, ACE, and ACE-lite.
The Bus Monitor enables full transaction-level visibility of traffic buses with a wide range of measurements, analytics and statistics gathering. All of these are run-time configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The modules can track transactions (e.g. trace) and automatically gather statistics to identify issues such as contention, peak traffic, and deadlock.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
The Bus Monitor enables full transaction-level visibility of traffic buses with a wide range of measurements, analytics and statistics gathering. All of these are run-time configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The modules can track transactions (e.g. trace) and automatically gather statistics to identify issues such as contention, peak traffic, and deadlock.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
Key features
- Full transaction and trace-level visibility of on-chip bus traffic
- Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
- Supports AXI, ACE, ACE-lite
- Run-time configurable
- Logic analyzer style controls and dependencies
Block Diagram
Tessent Bus Monitor block diagram
Benefits
- Accelerate SoC debug and SW development
- Identify and resolve hard-to-identify bugs significantly faster compared to traditional software-only solutions
- Root-cause performance degradations and memory corruption
- Better visibility and analytics
- Integrated part of the Tessent Embedded Analytics whole system solution
What’s Included?
- Parameterized soft core (Verilog RTL)
- Available UVM verification IP
- Optional Tessent SystemInsight IDE software
- Optional Tessent Embedded SDK software development kit
Specifications
Identity
Part Number
Tessent Bus Monitor
Vendor
Siemens Tessent Embedded Analytics
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about system monitoring IP cores
What is Tessent Bus Monitor?
Tessent Bus Monitor is a Monitoring IP core from Siemens Tessent Embedded Analytics listed on Semi IP Hub.
How should engineers evaluate this Monitoring?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Monitoring IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.