Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
- Samsung
- 28nm
- FDS
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
SMIC 0.11um USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock a…
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Master V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
The I3C library provides a bi-directional I/O driver designed for the I3C two-line interface.
1.2V GPIO library designed for the SVID three-line interface.
The 1.2V GPIO library provides an open-drain bi-directional I/O driver designed for the SVID three-line interface.
The (R)GMII library provides the combo driver / receiver and required support cells for (R)GMII signaling.
The RF libraries include analog signal pads and ESD protection components for RF applications.
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
10G Unmanaged Ethernet Switch IP core (10G UES) is an evolution of our 1G Unmanaged Ethernet Switch IP Core (UES).
Pulse Width Modulator (PWM) Controller
Dolphin Technology provides Pulse Width Modulator (PWM) IP which can easily modify the shape of the waveform during operation, ad…
Dolphin Technology provides Watchdog Timer (WDT) IP which is used to prevent system lockup if software becomes trapped in a deadl…
Dolphin Technology provides JTAG Controller (TAP) IP which enables access through the JTAG interface for building designs with ef…
Universal Synchnonous/Asynchronous Receiver Transmitter (UART/USART)
Dolphin Technology provides Universal Synchnonous/Asynchronous Receiver Transmitter (UART/USART) IP which allows the communicatio…
General Purpose Input/Output (GPIO) Controller
Dolphin Technology provides General Purpose I/O IP which cosists of up to 32 I/O ports that can be programmed individually for in…
PNU is a stand-alone Coprocessor capable of doing real-number computation on posit operands.
CRISP is a CPU Core built by integrating our PNU with 64-bit RISC-V Processor.